Overview

Merchant silicon has redefined data center and enterprise networking by delivering high-density switching capacity at disruptive cost points. Unlike custom ASICs, merchant silicon leverages broad ecosystems to achieve terabit-scale throughput, but real-world performance depends on fabric architecture, oversubscription ratios, and buffer design. This FAQ addresses pre-sales sizing and post-sales troubleshooting questions that network architects and procurement teams encounter when deploying merchant silicon-based switches in core and leaf-spine topologies.

Frequently Asked Questions

Q1: What is the maximum switching throughput capacity of a typical merchant silicon switch?

The maximum switching throughput of current-generation merchant silicon (e.g., Broadcom Tomahawk 5, Cisco Silicon One) ranges from 12.8 Tbps to 51.2 Tbps for a 32-port 800G or 64-port 400G configuration. This figure represents full-duplex line-rate forwarding across all ports simultaneously when configured with the correct optics. For example, a 25.6 Tbps device supports 64 x 400G ports at line rate. Always check the smaller packet forwarding rate (Mpps) for 64-byte frames, as that often becomes the bottleneck in real-world mixed-traffic environments.

Q2: How do I verify optical module compatibility (SFP/QSFP) for maximum throughput on merchant silicon?

Merchant silicon switches typically support IEEE-standard optics (SFP, SFP+, QSFP28, QSFP-DD) but require a transceiver compatibility matrix from the OEM. To achieve the advertised maximum throughput, use only coded optics that match the port's speed capability. For example, a 400G QSFP-DD port can also break out into 4x100G or 8x50G using fanout cables. To verify compatibility, enter the CLI command show interface transceiver (Cisco/NVIDIA) or show hw-module interface (Arista/Juniper). Third-party optics may require the command service unsupported-transceiver (vendor-dependent) but be aware that this voids some warranties and disables digital diagnostic monitoring (DDM) on certain platforms.

Q3: What backplane capacity and fabric oversubscription ratios should I expect from merchant silicon?

Merchant silicon designs fall into three backplane architectures: (1) single-chip with no oversubscription (1:1) up to ~12.8 Tbps, (2) dual-fabric with 2:1 oversubscription for 25.6 Tbps+ designs, and (3) multi-stage Clos fabrics with 3:1 to 4:1 oversubscription in dense 100G/400G topologies. Enterprise-class switches often advertise a backplane capacity of 2-4 Tbps with 1.5:1 oversubscription, while data center spine switches target 1:1 line rate. To calculate effective throughput: (Total backplane bandwidth) / (Number of front-panel ports x port speed). A 1:1 ratio guarantees non-blocking performance for all traffic patterns.

Q4: What are the key CLI commands to check throughput and port error statistics on merchant silicon?

The essential post-sales CLI commands for throughput verification are: show interface counters (displays packets-per-second and bits-per-second), show interfaces ethernet utilization (real-time bandwidth per port), show hardware buffer drops (identifies microburst drops), and show platform fabric utilization (backplane health). For merchant silicon from Broadcom, use bcmcmd 'show counter' after enabling shell access. Example: if show interface eth1/1 shows high CRC errors or pause frames, the issue is often SFP signal integrity or cable length, not silicon capacity. For stacking errors, show stack ports counters reveals misconfigured stack cable speeds.

Q5: How does merchant silicon throughput differ from previous generation custom ASIC switches?

Merchant silicon throughput now surpasses mid-range custom ASICs in raw Gbps per dollar, typically achieving 2-4x higher port density per RU. Legacy custom ASICs (pre-2018) offered deterministic low latency (under 300ns) but scaled poorly beyond 3.2 Tbps. Modern merchant silicon (2020+) delivers 12.8-51.2 Tbps with cut-through latency of 600-900ns. Key differences: merchant silicon uses shared buffer architectures (e.g., 16-32 MB dynamic buffers) while high-end custom ASICs use per-port dedicated buffers. For mixed packet sizes, merchant silicon maintains line rate up to 90% utilization; custom ASICs maintain line rate at 99%+ but cost 5-8x more per 10G port.

Q6: How do I configure stacking interfaces to maximize aggregated throughput on merchant silicon switches?

To maximize stacking throughput, use dedicated stack ports (e.g., 4x100G or 2x400G) rather than front-panel Ethernet ports repurposed for stacking. Configure stack links as a port-channel (LAG) to avoid spanning-tree blocking. On merchant silicon, the stacking bandwidth is shared between control plane and data plane. Example configuration (Cisco-like): stack-port 1/1 speed 100G force, then stack-group 1 port-channel 100. Verify stack link utilization with show stack bandwidth. If stack throughput drops below 80% of configured speed, check for mismatched MTU — all stack members must have identical jumbo frame support (typically 9216 bytes). For virtual chassis stacking, ensure the stack ring is complete (no open chain) to avoid cut-through latency penalties.

Q7: What is the troubleshooting process for redundant power supply failover affecting throughput?

Merchant silicon switches experiencing a PSU failover should maintain 100% throughput if the remaining PSU(s) have sufficient wattage headroom. First, verify with show environment power that each PSU is rated for the full system power (e.g., 1100W AC per unit). If throughput drops after a PSU fails, check for power budgeting: some merchant silicon designs limit fabric speed in low-power mode. Recovery steps: (1) show power redundancy — confirm mode is set to "redundant" not "combined"; (2) physically reseat the failed PSU; (3) if traffic loss persists, issue power cycle fabric (vendor-specific). For hot-swap events, the switch may take 300-500ms to renegotiate PCIe links between the silicon and fabric expanders — this can appear as a microburst loss. Use show platform power history to log failover events.

Q8: Can merchant silicon achieve line-rate throughput with all ACLs and QoS policies enabled?

Yes, modern merchant silicon (Broadcom Trident 4/5, Jericho 2+) achieves line-rate throughput with up to 4,000 ingress ACL entries and 8-queue QoS enabled, using ternary content-addressable memory (TCAM) resources. However, enabling both IPv4 and IPv6 ACLs simultaneously can exceed TCAM capacity (typically 8k-16k entries), forcing traffic to the slower CPU path. To test line-rate preservation, use the command show tcam utilization before and after applying policies. For merchant silicon without look-aside memory, features like VXLAN routing with ACLs may degrade throughput by 15-30%. Best practice: apply port-based ACLs rather than VLAN-based ACLs, and use sFlow sampling instead of full port mirroring for monitoring throughput-heavy links.